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hm628512ci series wide temperature range version 4 m sram (512-kword 8-bit) ade-203-1211b (z) rev. 2.0 jul. 23, 2001 description the hitachi hm628512ci is a 4-mbit static ram organized 512-kword 8-bit. hm628512ci series has realized higher density, higher performance and low power consumption by employing cmos process technology (6-transistor memory cell). the hm628512ci series offers low power standby power dissipation; therefore, it is suitable for battery backup systems. it has packaged in 32-pin sop, 32-pin tsop ii and 32-pin dip. features single 5 v supply access time: 70 ns (max) power dissipation ? active: 10 mw/mhz (typ) ? standby: 4 w (typ) completely static memory. no clock or timing strobe required equal access and cycle times common data input and output: three state output directly ttl compatible: all inputs and outputs battery backup operation operating temperature: C40 to +85?c
hm628512ci series 2 ordering information type no. access time package hm628512clpi-7 70 ns 600-mil 32-pin plastic dip (dp-32) hm628512clfpi-7 70 ns 525-mil 32-pin plastic sop (fp-32d) HM628512CLTTI-7 70 ns 400-mil 32-pin plastic tsop ii (ttp-32d) hm628512clrri-7 70 ns 400-mil 32-pin plastic tsop ii reverse (ttp-32dr)
hm628512ci series 3 pin arrangement 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 ss a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v v a15 a17 we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 cc 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 ss v a15 a17 we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v cc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 a18 a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o0 i/o1 i/o2 v ss v a15 a17 we a13 a8 a9 a11 oe a10 cs i/o7 i/o6 i/o5 i/o4 i/o3 cc (top view) 32-pin dip 32-pin sop 32-pin tsop 32-pin tsop (reverse) (top view) (top view) pin description pin name function a0 to a18 address input i/o0 to i/o7 data input/output cs chip select oe output enable we write enable v cc power supply v ss ground
hm628512ci series 4 block diagram i/o0 i/o7 cs we oe a3 a2a1a0 a6 a5 v v cc ss row decoder memory matrix 2,048 2,048 column i/o column decoder input data control timing pulse generator read/write control a4 a7 a11 a9 a8 a15 a18 a10 a13 a17 a16 a14 a12 lsb msb lsb msb
hm628512ci series 5 function table we cs oe mode v cc current dout pin ref. cycle h not selected i sb , i sb1 high-z h l h output disable i cc high-z h l l read i cc dout read cycle l l h write i cc din write cycle (1) l l l write i cc din write cycle (2) note: : h or l absolute maximum ratings parameter symbol value unit power supply voltage v cc C0.5 to +7.0 v voltage on any pin relative to v ss v t C0.5* 1 to v cc + 0.3* 2 v power dissipation p t 1.0 w operating temperature topr C40 to +85 c storage temperature tstg C55 to +125 c storage temperature under bias tbias C40 to +85 c notes: 1. v t min: C3.0 v for pulse half-width 30 ns. 2. maximum voltage is 7.0 v. recommended dc operating conditions (ta = C40 to +85c) parameter symbol min typ max unit supply voltage v cc 4.5 5.0 5.5 v v ss 000v input high voltage v ih 2.4 v cc + 0.3 v input low voltage v il C0.3 *1 0.6 v note: 1. v il min: C3.0 v for pulse half-width 30 ns.
hm628512ci series 6 dc characteristics parameter symbol min typ* 1 max unit test conditions input leakage current |i li | 1 a vin = v ss to v cc output leakage current |i lo |1a cs = v ih or oe = v ih or we = v il , v i/o = v ss to v cc operating power supply current: dc i cc 1.5 3 ma cs = v il , others = v ih /v il , i i/o = 0 ma operating power supply current i cc1 7 25 ma min cycle, duty = 100% cs = v il , others = v ih /v il i i/o = 0 ma operating power supply current i cc2 2 5 ma cycle time = 1 s, duty = 100% i i/o = 0 ma, cs 0.2 v v ih 3 v cc C 0.2 v, v il 0.2 v standby power supply current: dc i sb 0.1 0.5 ma cs = v ih standby power supply current (1): dc i sb1 0.8* 2 20* 2 a vin 3 0 v, cs 3 v cc C 0.2 v output low voltage v ol 0.4 v i ol = 2.1 ma output high voltage v oh 2.4 v i oh = C1.0 ma notes: 1. typical values are at v cc = 5.0 v, ta = +25c and specified loading, and not guaranteed. 2. this characteristics is guaranteed only for l-version. capacitance (ta = +25c, f = 1 mhz) parameter symbol typ max unit test conditions input capacitance* 1 cin 8 pf vin = 0 v input/output capacitance* 1 c i/o 10* 2 pf v i/o = 0 v note: 1. this parameter is sampled and not 100% tested. 2. c i/o max = 12 pf only for hm628512clpi series.
hm628512ci series 7 ac characteristics (ta = C40 to +85c, v cc = 5 v 10%, unless otherwise noted.) test conditions input pulse levels: 0.4 v to 2.4 v input rise and fall time: 5 ns input and output timing reference levels: 1.5 v output load: 1 ttl gate + c l (100 pf) (including scope and jig) read cycle hm628512ci -7 parameter symbol min max unit notes read cycle time t rc 70 ns address access time t aa 70ns chip select access time t co 70ns output enable to output valid t oe 35ns chip selection to output in low-z t lz 10 ns 2 output enable to output in low-z t olz 5 ns 2 chip deselection to output in high-z t hz 0 25 ns 1, 2 output disable to output in high-z t ohz 0 25 ns 1, 2 output hold from address change t oh 10 ns
hm628512ci series 8 write cycle hm628512ci -7 parameter symbol min max unit notes write cycle time t wc 70 ns chip selection to end of write t cw 60 ns 4 address setup time t as 0 ns 5 address valid to end of write t aw 60 ns write pulse width t wp 50 ns 3, 12 write recovery time t wr 0 ns 6 we to output in high-z t whz 0 25 ns 1, 2, 7 data to write time overlap t dw 30 ns data hold from write time t dh 0ns output active from output in high-z t ow 5 ns 2 output disable to output in high-z t ohz 0 25 ns 1, 2, 7 notes: 1. t hz , t ohz and t whz are defined as the time at which the outputs achieve the open circuit conditions and are not referred to output voltage levels. 2. this parameter is sampled and not 100% tested. 3. a write occurs during the overlap (t wp ) of a low cs and a low we . a write begins at the later transition of cs going low or we going low. a write ends at the earlier transition of cs going high or we going high. t wp is measured from the beginning of write to the end of write. 4. t cw is measured from cs going low to the end of write. 5. t as is measured from the address valid to the beginning of write. 6. t wr is measured from the earlier of we or cs going high to the end of write cycle. 7. during this period, i/o pins are in the output state so that the input signals of the opposite phase to the outputs must not be applied. 8. if the cs low transition occurs simultaneously with the we low transition or after the we transition, the output remain in a high impedance state. 9. dout is the same phase of the write data of this write cycle. 10. dout is the read data of next address. 11. if cs is low during this period, i/o pins are in the output state. therefore, the input signals of the opposite phase to the outputs must not be applied to them. 12. in the write cycle with oe low fixed, t wp must satisfy the following equation to avoid a problem of data bus contention. t wp 3 t dw min + t whz max
hm628512ci series 9 timing waveforms read timing waveform ( we = v ih ) t aa t co t rc t lz t oe t olz t hz t ohz valid data address cs oe dout t oh
hm628512ci series 10 write timing waveform (1) ( oe clock) t wc t cw t wp t as t ohz t dw t dh t aw t wr *8 address oe cs we dout din valid data
hm628512ci series 11 write timing waveform (2) ( oe low fixed) address cs we dout din t wc t cw t wr t aw t wp t as t whz t ow t oh t dw t dh *11 *9 *10 *8 valid data
hm628512ci series 12 low v cc data retention characteristics (ta = C40 to +85c) parameter symbol min typ max unit test conditions* 2 v cc for data retention v dr 2v cs 3 v cc C 0.2 v, vin 3 0 v data retention current i ccdr 0.8* 3 20* 1 a v cc = 3.0 v, vin 3 0 v cs 3 v cc C 0.2 v chip deselect to data retention time t cdr 0 ns see retention waveform operation recovery time t r t rc * 4 ns notes: 1. for l-version and 10 a (max.) at ta = C40 to +40c. 2. cs controls address buffer, we buffer, oe buffer, and din buffer. in data retention mode, vin levels (address, we , oe , i/o) can be in the high impedance state. 3. typical values are at v cc = 3.0 v, ta = +25c and specified loading, and not guaranteed. 4. t rc = read cycle time. low v cc data retention timing waveform ( cs controlled) v cc 4.5 v 2.4 v 0 v cs t cdr t r cs 3 v cc ?0.2 v v dr data retention mode
hm628512ci series 13 package dimensions hm628512clpi series (dp-32) hitachi code jedec eiaj mass (reference value) dp-32 conforms 5.1 g 0.51 min 2.54 min 5.08 max 0.25 + 0.11 ?0.05 2.54 0.25 0.48 0.10 0 ?15 41.90 42.50 max 13.4 13.7 max 15.24 32 17 1 16 2.30 max 1.20 as of january, 2001 unit: mm
hm628512ci series 14 package dimensions (cont.) hm628512clfpi series (fp-32d) hitachi code jedec eiaj mass (reference value) fp-32d conforms 1.3 g *dimension including the plating thickness base material dimension 0.15 m *0.40 0.08 20.45 1.00 max 1.27 11.30 1.42 3.00 max *0.22 0.05 20.95 max 32 17 1 16 0 ?8 0.80 0.20 14.14 0.30 0.10 0.38 0.06 + 0.12 ?0.10 0.15 0.20 0.04 as of january, 2001 unit: mm
hm628512ci series 15 package dimensions (cont.) HM628512CLTTI series (ttp-32d) hitachi code jedec eiaj mass (reference value) ttp-32d conforms 0.51 g *dimension including the plating thickness base material dimension 1.27 0.21 m *0.42 0.08 0.10 10.16 20.95 21.35 max 17 16 32 1 1.20 max 0 ?5 0.13 0.05 *0.17 0.05 11.76 0.20 0.50 0.10 1.15 max 0.80 0.40 0.06 0.125 0.04 as of january, 2001 unit: mm
hm628512ci series 16 package dimensions (cont.) hm628512clrri series (ttp-32dr) hitachi code jedec eiaj mass (reference value) ttp-32dr conforms 0.51 g *dimension including the plating thickness base material dimension 1.27 0.21 m *0.42 0.08 0.10 10.16 20.95 21.35 max 16 17 1 32 1.20 max 0 ?5 0.13 0.05 *0.17 0.05 11.76 0.20 0.50 0.10 1.15 max 0.80 0.40 0.06 0.125 0.04 as of january, 2001 unit: mm
hm628512ci series 17 cautions 1. hitachi neither warrants nor grants licenses of any rights of hitachis or any third partys patent, copyright, trademark, or other intellectual property rights for information contained in this document. hitachi bears no responsibility for problems that may arise with third partys rights, including intellectual property rights, in connection with use of the information contained in this document. 2. products and product specifications may be subject to change without notice. confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. hitachi makes every attempt to ensure that its products are of high quality and reliability. however, contact hitachis sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. design your application so that the product is used within the ranges guaranteed by hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the hitachi product. 5. this product is not designed to be radiation resistant. 6. no one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from hitachi. 7. contact hitachis sales office for any questions regarding this document or hitachi semiconductor products. hitachi, ltd. semiconductor & integrated circuits nippon bldg., 2-6-2, ohte-machi, chiyoda-ku, tokyo 100-0004, japan tel: (03) 3270-2111 fax: (03) 3270-5109 copyright ?hitachi, ltd., 2001. all rights reserved. printed in japan. hitachi asia ltd. hitachi tower 16 collyer quay #20-00 singapore 049318 tel : <65>-538-6533/538-8577 fax : <65>-538-6933/538-3877 url : http://semiconductor.hitachi.com.sg url http://www.hitachisemiconductor.com/ hitachi asia ltd. (taipei branch office) 4/f, no. 167, tun hwa north road hung-kuo building taipei (105), taiwan tel : <886>-(2)-2718-3666 fax : <886>-(2)-2718-8180 telex : 23222 has-tp url : http://www.hitachi.com.tw hitachi asia (hong kong) ltd. group iii (electronic components) 7/f., north tower world finance centre, harbour city, canton road tsim sha tsui, kowloon hong kong tel : <852>-(2)-735-9218 fax : <852>-(2)-730-0281 url : http://semiconductor.hitachi.com.hk hitachi europe gmbh electronic components group dornacher stra? 3 d-85622 feldkirchen postfach 201,d-85619 feldkirchen germany tel: <49> (89) 9 9180-0 fax: <49> (89) 9 29 30 00 hitachi europe ltd. electronic components group whitebrook park lower cookham road maidenhead berkshire sl6 8ya, united kingdom tel: <44> (1628) 585000 fax: <44> (1628) 585200 hitachi semiconductor (america) inc. 179 east tasman drive san jose,ca 95134 tel: <1> (408) 433-1990 fax: <1>(408) 433-0223 for further information write to: colophon 5.0

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